The present invention relates to a manufacturing process of a semiconductor device such as IC, a sputtering target for a metal silicide wiring pattern and a manufacturing process for the sputtering target.
FIG. 4 shows a conventional process for forming an FET gate on a silicon substrate and for contacting the gate with a wiring pattern on an upper layer via a contact hole. As shown in FIG. 4(a), 7 through 15 nm in thickness of a gate oxide layer 2 is formed on a surface of a silicon substrate 1 through the thermal oxidation process, and poly-silicon is deposited by CVD (chemical vapor deposition) and doped with phosphorus (P) or arsenic (As) in an ion implantation process in order to form a doped poly-silicon layer 3. Then, a metal silicide having a high melting point such as tungsten silicide (WSi) is formed on the poly-silicon layer in CVD or the sputtering method, thereby forming a first wiring pattern layer 4.
A gate G is, as shown in FIG. 4(b), formed on the stacked layers through the photo lithography process and an insulator film 5 is formed by thermal oxidation at 800 to 900.degree. C.
Subsequently, as shown in FIG. 4(c), BPSG (borophosphosilicate glass) is deposited by CVD and a first insulator layer 6 is formed through the thermal oxidation. A contact hole 7 is opened through the first insulator layer 6 and the insulator film 5 on the gate. A poly-silicon film is formed by CVD, as shown in FIG. 4(c), and phosphorus (P) is diffused or arsenic (As) is doped by ion implantation into the poly-silicon film to form a second wiring pattern layer 8. Then, an electrode pattern is formed on the second wiring pattern layer 8 in a photo lithography process. Finally, as shown in FIG. 4(e), a BPSG layer is formed by CVD and the formed layer is thermally treated to form a second insulator layer 9.
In the conventional wiring process, however, since the thermal treatment for forming the second insulator layer 9 causes diffusion of the dopant such as phosphorus (P) or arsenic (As) into the first wiring pattern layer 4 from the second wiring pattern layer 8, it increases the contact resistance between the first and second wiring pattern layers 4, 8, and the predetermined transistor properties cannot be achieved due to failing of the ohmic contact.
Further, when the first wiring pattern layer 4 is formed in the sputtering method, abnormal discharge occurs due to charge-up of silicon included in the sputtering target. Thus the silicon is scattered on the wafer as particles, and they may cause an unnecessary short-circuit. The sputtering target for forming the first wiring pattern layer 4 is a mixture of tungsten (W) and silicon (Si) whose molar ratio W:Si is 1:2.6 to 1:2.8. The molar ratio of tungsten silicide (WSi.sub.2) as a pure compound is 1:2. The sputtering target is produced by mixing tungsten silicide with silicon particles and by baking the mixture under high-pressure. Since the mixed silicon particles has exceedingly low conduction, it causing charge-up in a well-used DC magnetron sputtering method.